Mixer arrangement

ABSTRACT

Mixer arrangement suitable for use in a television receiver operating in the UHF band is disclosed. The arrangement contains a variable gain amplifier stage including a first field effect transistor whose first principal terminal referred to as drain is biased via a load by a DC supply source and whose control terminal referred to as gate receives a first RF signal at a first frequency which is modulated by a second signal at a second frequency applied to the amplifier stage through a variable resistor T 2  such that the output signal of the amplifier stage which is available at the first principal drain terminal of the first transistor is formed from the mixture of the first and the second signal. The second signal OL is applied via the variable resistor to the first principal drain terminal of the first transistor T 1  resulting in the variation of the amplifier gain occurring from the modulation of the load constituted by the biasing load above and the variable resistor. The second principal terminal referred to as source of the first transistor is directly brought to a reference potential.

BACKGROUND OF THE INVENTION

The invention relates to a mixer arrangement comprising a variable gainamplifier stage including a first field effect transistor T₁ whose firstprincipal terminal referred to as drain is biased via a load T₃ by a DCsupply source V_(DD) and whose control terminal referred to as gatereceives a first RF signal to be mixed with a second signal OL appliedto the first field effect transistor T₁ through a variable resistor T₂,such that the output signal IF of the amplifier stage available at thefirst principal drain terminal of the first transistor T₁ is formed fromthe mixture of the first and the second signal.

This arrangement is used for processing, for example, hyperfrequencysignals in the field of receiving television transmission signals.

Such a mixer arrangement is known in the prior art from the publicationby Rory Van Tuyl in "1980 IEEE Solid State Circuits Conference" in theissue of "ISSCC 80, Thursday, Feb. 14, Session X=Microwave Circuits,pages 118, 119" entitled "A monolithic GaAS FET RF Signal GenerationChip".

This publication particularly describes a mixer arrangement comprisingan amplifier stage comprising a first field effect transistorconstituting the actual amplifier section. The control or gate electrodeof the first transistor receives a first signal at a first frequencywhich is mixed by a second signal at a second frequency. This secondsignal is applied to the source of the first transistor by means of asecond field effect transistor used as a variable resistor. The drain ofthe first transistor, referred to as amplifier is biased from a DCsupply through a load, and its source is biased with respect to groundby a third transistor being arranged as a current source, resulting inthis amplifier stage functioning as a negative feedback amplifier. Themixture of the first and the second signal is available at the drainelectrode of the first transistor, and constitutes the output signal ofthe variable gain amplifier. The third transistor, utilized as a currentsource, has a high impedance in order to interfere as little as possiblein the mixer function. The second transistor, used as a variableresistor receives the signal from a local oscillator at its gateelectrode and is given a condition in which its drain-source voltage isequal to zero.

The document cited above particularly describes a double and balancedarrangement of this mixer, permitting improvement of the isolationbetween the gates; that is to say, obtaining a satisfactory isolationbetween the signal from the local oscillator, the input signal of themixer and the output signal.

The mixer circuit described in the document cited above has two seriousdrawbacks. The first drawback is that the noise factor of this circuitis very high. This is due to the presence of noisy elements applied tothe source of the first transistor referred to as amplifier. A noisyelement is, inter alia, the transistor used as a current source. Thesecond drawback is that the satisfactory biasing conditions of theamplifier transistor are difficult to obtain.

SUMMARY OF THE INVENTION

The object of the invention is to obviate these drawbacks.

This object is achieved by means of an arrangement as described in theopening paragraph, and is characterized in that the second signal OL isapplied through the variable resistor T₂ to the first principal drainterminal of the first transistor T₁ for modulating the load constitutedby T₃ and T₂ resulting in a variation of the amplifier gain.

This arrangement may further be characterized in that the secondprincipal terminal referred to as source of the first transistor T₁ isdirectly connected to a reference potential V_(M).

The arrangement of the mixer type in accordance with the invention thushas, inter alia, the following advantages:

(a) the noise factor of this mixer is considerably improved incomparison with that of the prior art mixer;

(b) the amplifier stage is biased in a very simple manner;

(c) the conversion gain is very satisfactory and;

(d) the supply voltage required to make the novel arrangement functionis lower than that with the prior art arrangement, so that its powerconsumption is reduced.

The mixer arrangement according to the invention may include twoidentical variable gain amplifiers which are coupled to each other andreceive the second signal OL and its complementary signal OL and supplythe output signal IF and its complementary signal IF, respectively.

In a special embodiment of this arrangement, the second signal OL andits complementary signal OL are obtained from an oscillator, referred toas local oscillator, at outputs of an antiphase amplifier comprising adifferential amplifier, an input of which receives the signal from thelocal oscillator.

With regard to the prior art arrangement, the invention further improvesthe isolation between the input signal RF, the output signal IF and thelocal oscillator signal.

DESCRIPTION OF THE DRAWINGS

The invention will now be described in greater detail with reference tothe accompanying drawings in which

FIG. 1 shows the elementary mixer stage according to the invention;

FIG. 2 shows the mixer stage in a particular embodiment;

FIG. 3 shows an equivalent circuit diagram of the mixer stage accordingto the invention;

FIG. 4 shows an arrangement consisting of two coupled elementary mixerstages associated with an antiphase amplifier.

DETAILED DESCRIPTION

As is shown in FIG. 1, the amplifier stage on which the mixer concept isbased is an inverter stage. It is constituted by a first field effecttransistor T₁ whose first principal terminal 1, referred to as drainelectrode, is biased from a DC voltage V_(DD) via a load T₃ and whosesecond principal terminal 2 referred to as source electrode is directlyconnected to a DC reference potential V_(M), for example, ground. Thecontrol electrode 5, referred to as the gate electrode, receives a firstsignal RF at a first frequency referred to as reference frequency. Thissignal RF may be an antenna signal received at, for example, an aerialfor hyperfrequencies.

The voltage gain A of this inverter stage is given by the relation (1):

    A=-R×g.sub.m                                         (1)

In this relation g_(m) is the transconductance of the transistor T₁ andR is the value of its total load.

To realize the function of the mixer with the aid of this amplifierstage, the voltage gain A is modulated. This modulation is generated inthe arrangement according to the invention by modulation of the load R.

The modulation of the load R is obtained by variation of a variableresistor T₂ by means of which a second signal OL at a second frequencyis applied to the first principal terminal 1 (drain) of the transistorT₁.

This variable resistor T₂ can be advantageously constituted by a fieldeffect transistor, one of the principal terminals 4 of which is coupledto the reference potential V_(M) through a DC isolating capacitor C,whose second principal terminal 3 is connected to the drain electrode 1of the amplifier transistor T₁ and whose control electrode 6 (gate)receives the second signal OL. This signal may originate from a localoscillator.

Thus, no direct current flows through the transistor T₂ which is used asa variable resistor: it is biased in the triode zone. The signal OLapplied to the gate electrode 6 will thus not entail any variation inthe bias of the transistor T₁. This allows to connect the transistor T₂directly to the first principal terminal 1 (drain) of the amplifiertransistor T₁ and to eventually bias this transistor through a load T₃of the resistive type.

This principle is fundamentally different from that used in the priorart arrangement in which the voltage gain is a function of theresistance value of a load at the drain, a variable source resistor andthe impedance value of a current source at the source of a transistorconstituting the amplifier stage, the latter being of the negativefeedback amplifier type, while the variation in gain is obtained bymodulation of the variable source resistor with the local oscillatorsignal.

According to the present invention, the grounding of the source 2 of theamplifier transistor results in a simpler assembly, a simpler biasingand a considerable improvement of the noise factor; and the applicationof the second signal OL to the drain 1 of the amplifier transistorallows for estimation of the gain by means of a very simple calculation,thus yielding a very simple and less costly design of the circuit.

The output signal IF, formed by mixing the first signal RF and thesecond signal OL, is available at the first principal terminal 1 (drain)of the amplifier transistor T₁. The conversion gain A is verysatisfactory, and the isolation between the first signal, referred to asreference signal RF, and the second signal OL supplied, for example, bya local oscillator, is improved with respect to the prior artarrangement because, in the assembly according to the invention, it isnot possible for the signal OL to radiate through to the gate electrodeof the transistor T₁.

FIG. 2 shows a modification of the arrangement of the mixer stageaccording to the invention in which the load T₃ is constituted by afield effect transistor arranged as a current source.

A simplified equivalent circuit diagram of the afore-mentionedelementary mixer stage is shown in FIG. 3. This diagram permitseffecting a first order calculation of the conversion gain of theamplifier stage according to the invention.

This conversion gain A is given by the relation (2):

    A=-(R.sub.3 ·R.sub.OL)(R.sub.OL +R.sub.3 +g.sub.d R.sub.OL R.sub.3).sup.-1 ×g.sub.m                            (2)

in which R_(OL) represents the resistance of the transistor utilized asa variable resistor T₂, R₃ represents the resistance value of the loadT₃ and g_(d) represents the conductance of the amplifier transistor T₁at its drain electrode.

This relation shows that the gain of the arrangement according to theinvention can be calculated and optimized in a simple manner as afunction of the dimensioning of the transistors.

FIG.4 shows an embodiment of a balanced mixer circuit, including twocoupled elementary mixer stages according to the invention, forming twobranches.

The first branch comprises a first mixer stage constituted bytransistors T₁, T₂, T₃, and the second branch comprises a second mixerstage constituted by transistors T'₁, T'₂, T'₃, respectively identicalto transistors T₁, T₂, T₃.

These two branches are coupled through the DC-isolation capacitor C ofeach of the transistors T₂ and T'₂ used as variable resistors in the twomixer stages.

Each of these mixer stages receives the input reference signal RF at thecontrol electrodes or gates (5, 15) of the amplifier transistors T₁ andT'₁.

One of these mixer stages supplies the output signal IF at the firstprincipal terminal 1 (drain) of the amplifier transistor, for exampleT₁, and receives the second signal OL at the control terminal 6 (gate)of the transistor used as a variable resistor, for example T₂.

The other mixer stage supplies the complementary output signal IF at thefirst principal terminal 11 (drain) of the amplifier transistor T'₁ andreceives the complementary signal OL of the second signal at the controlterminal 16 (gate) of the transistor used as a variable resistor T'₂.

In order to supply the second signal OL and its complementary signal OLin an appropriate manner, a differential antiphase amplifier is added tothe aforementioned arrangement, and it is intended to supply the secondsignal OL and its complementary signal OL from the signal V_(OL), whichis directly supplied by, for example, a local oscillator.

This differential amplifier comprises two branches which are constitutedby a field effect transistor T₄, whose drain electrode 21 is coupled tothe supply voltage V_(DD) via the load R₄ on the one hand, and by afield effect transistor T'₄ whose drain electrode 31 is coupled to thevoltage V_(DD) via the load R'₄ on the other hand. The source electrodes22 and 32 of the transistors T₄ and T'₄ are coupled to the drainelectrode 51 of a field effect transistor T₅ arranged in a currentsource, the short-circuited source electrode 52 and the gate electrode53 are brought to a potential -V_(SS) <V_(M).

The signal V_(OL) from the local oscillator is applied, for example, tothe control electrode 23 of the transistor T₄ of the differentialamplifier by means of a circuit including the capacitor C₅ arranged inseries with the input and the resistor R₅ arranged between the controlelectrode (gate) of the transistor T₄ and a d.c. potential -VG₂ so that:

    -V.sub.SS <-VG.sub.2 <V.sub.M

The differential amplifier is DC-balanced by connecting a resistor R'₅and a capacitor C'₅ arranged in parallel and connected to the potential-VG₂, to the control electrode 33 of the transistor T'₄ of the secondbranch.

The output signal OL and its complementary signal OL of thisdifferential antiphase amplifier are applied by means of the capacitorsC₂ and C'₂ to the control electrodes 6 and 16 (gates) of the transistorsT₂ and T'₂ of the coupled mixer stages.

The biasing and balancing of the arrangement includes further, theconnection of resistors R₂ and R'₂ between the control electrodes 6 and16 of these transistors T₂ and T'₂ and a d.c. potential VG₁, VG₁ beingchosen such that

    V.sub.M <VG.sub.1 <V.sub.DD

as well as the connection of the resistors R₁ and R'₁ between thecontrol electrodes 5 and 15 of the transistors T₁ and T'₁ and thepotential -VG₂.

The circuit arrangement described in this embodiment, i.e. the coupledmixer stages and the differential antiphase amplifier, can be integratedadvantageously on a gallium arsenide substrate whose properties areparticularly favorable for realizing hyperfrequency circuits, andparticularly circuits for the UHF band.

The field effect transistors used may be of the depletion type (i.e.normally, conducting in the absence of the gate-source signal),

Tables I and II show the widths of the transistor gates and the valuesof the resistors used in the conditions in which the supply voltages arethe following:

    ______________________________________                                        V.sub.DD = + 4 V                                                                           - V.sub.SS = - 3 V                                               V.sub.G.sbsb.1 = + 1 V                                                                     - V.sub.G.sbsb.2 = - 1 V                                         V.sub.M = 0 V (ground)V.sub.T ≃ - 2 V                           ______________________________________                                    

in which V_(T) is the pinch-off voltage of the field effect transistors.

In the integration of the aforementioned circuit arrangement on agallium arsenide substrate, the capacitor C, disposed between thetransistors T₂ and T'₂ and ground and having a high value of the orderof 1 nF, may not be integrated.

The described circuit arrangement has the following performances:

Conversion gain G_(C) ≃4 dB

Power consumption P≃75 mW.

As described hereinbefore, this mixer circuit may be used inhyperfrequency applications and in the UHF band, and more specificallyin the processing of signals provided by an aerial or an head endstation used for the reception of television transmissions in the UHFband. In this application the reference signal RF is the signal providedby the aerial at a first frequency f₁ between 460 and 860 MHz. The localoscillator signal OL is provided at a second frequency f₂ between 430and 830 MHz.

The circuit described has the advantage of a good performance, and it issimple and can be integrated, which is very favourable, for such anapplication of the circuit intended for the general consumer market.

                  TABLE I                                                         ______________________________________                                        Transistors  Gate widths (μm)                                              ______________________________________                                        T.sub.3, T'.sub.3                                                                          48 μm                                                         T.sub.2, T'.sub.2                                                                          14 μm                                                         T.sub.1, T'.sub.1                                                                          24 μm                                                         T.sub.4, T'.sub.4                                                                          24 μm                                                         T.sub.5      24 μm                                                         ______________________________________                                    

                  TABLE II                                                        ______________________________________                                        Resistors and capacitors                                                                              Values                                                ______________________________________                                        R.sub.1, R'.sub.1        20k Ω                                          R.sub.2, R'.sub.2        20k Ω                                          R.sub.4                   1k Ω                                          R'.sub.4                1,1k Ω                                          C.sub.5, C'.sub.5         1 pF                                                C.sub.2, C'.sub.2         1 pF                                                R.sub.5, R'.sub.5        20k Ω                                          C                         1 nF                                                ______________________________________                                    

What is claimed is:
 1. A mixer arrangement comprising:a field effecttransistor T₁ having a drain connected through a resistance element to afirst terminal of a DC voltage supply V_(DD) and a source connected to asecond reference terminal V_(M) of said voltage supply, and having agate connected to receive an RF signal; and, a variable resistanceelement T₂ electrically connected between said drain and source, saidvariable resistance element having a resistance which varies inaccordance with a local oscillator signal applied to a control terminalof said variable resistance element, whereby the total gain of saidfield effect transistor measured between said gate and drain is variedas the shunt impedance provided by said variable resistance elementvaries.
 2. An arrangement as claimed in claim 1, wherein the variableresistance element T₂ and a DC isolating capacitor C are connected inseries between the drain terminal of the transistor T₁ and the referenceterminal V_(M).
 3. An arrangement as claimed in claim 1, wherein thesource of the transistor T₁ is directly connected to the referencepotential V_(M) terminal.
 4. An arrangement as claimed in claim 3,wherein the drain connected resistance element is constituted by a fieldeffect transistor.
 5. An arrangement as claimed in claim 3, wherein thedrain connected resistance element is constituted by a resistor.
 6. Anarrangement as claimed in claim 5, wherein the variable resistanceelement is constituted by a field effect transistor arranged as atriode.
 7. A mixer arrangement comprising:a first field effecttransistor amplifier having a gate connected to receive an RF signal, adrain connected through a DC load element to a first terminal of a DCvoltage supply, and a source connected to a second common terminal ofsaid DC voltage supply; and, a second field effect transistor having adrain and source capacitively coupled as a shunt impedance across saidfirst field effect transistor source and drain, and a gate connected toreceive a local oscillator signal, whereby the total impedance seen bysaid first transistor drain varies in accordance with said localoscillator signal, varying the total gain of said amplifier.
 8. Abalanced mixer arrangement comprising:first and second field effecttransistors connected as amplifiers, each transistor having a commongate connection connected to receive an RF signal, each amplifier havinga load resistance connecting a respective drain connection to a firstterminal of a DC voltage supply, and each having common sourceconnections connected to a second reference terminal of said DC voltagesupply; first and second shunt transistors capacitively connectedbetween the drain and source connection of said first and second fieldeffect transistors which vary the gain of said first and secondtransistors connected as amplifiers in accordance with a signal appliedto each gate connection; and a differential amplifier having an inputreceiving a local oscillator signal, and first and second complementaryoutputs connected to gate connections of said first and second shunttransistors.